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col-lg-12"><h2>Announcing<br/><span>MARS Chiplet</span><br/> Platform.</h2><p class="slider_textLg__JeDr1 block-title ">Learn what the excitement of MARS Chiplet platform is about.</p><a href="#bg-video" data-target=".donate-options" class="scroll-to-target thm-btn">Learn More</a></div></div></div></div><div class="swiper-slide"><div class="image-layer" style="background-image:url(/_next/static/media/slider-1-1.c3472cc4.jpg)"></div><div class="container"><div class="justify-content-end row"><div class="text-right col-lg-7"><h2>Working on<br/><span> Next Generation</span><br/> Technologies.</h2></div></div></div></div><div class="swiper-slide"><div class="image-layer" style="background-image:url(/_next/static/media/joshua-sortino-LqKhnDzSF-8-unsplash.49faa3a6.jpg)"></div><div class="container"><div class="justify-content-end row"><div class="text-right col-lg-7"><h2><span>SMARTNIC</span><br/> Data Center And Storage</h2></div></div></div></div><div class="swiper-slide"><div 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class="video-card_background__ajbIq"><div class="video-card_bgImg1__6uHn1"></div><div class="video-card_circuit__m_zo4"></div><div class="custom-container container"><div class="swiper"><div class="swiper-wrapper"><div class="swiper-slide"><div class="video-card_mainCard__YvhQN" style="background-image:url(/_next/static/media/cristiano-firmani-tmTidmpILWw-unsplash.09d799c5.jpg)"><div style="height:100%" class="align-items-center row"><div class="col-lg-3"><div class="video-card-two__box mt-2"><img src="/_next/static/media/Ellipse 1.aa094e05.png" alt="" class="video-card_bgVideo__gPE7T"/><span class="video-card-two__box-btn video-popup"><i class="fa fa-play"></i></span></div></div><div class="col-lg-4"><h3>NVMe over Fabric (NVME-oF)</h3></div><div class="col-lg-5"><p class="text-white line-clamp-3">NVMe over Fabric (NVME-oF) demonstration using RDMA with DreamBig Semiconductor chiplet based MARS SmartNIC</p></div></div></div></div><div class="swiper-slide"><div class="video-card_mainCard__YvhQN" style="background-image:url(/_next/static/media/martin-martz-Wa-3T6d0rBo-unsplash.759ed575.jpg)"><div style="height:100%" class="align-items-center row"><div class="col-lg-3"><div class="video-card-two__box mt-2"><img src="/_next/static/media/Ellipse 1.aa094e05.png" alt="" class="video-card_bgVideo__gPE7T"/><span class="video-card-two__box-btn video-popup"><i class="fa fa-play"></i></span></div></div><div class="col-lg-4"><h3>MARS SmartNIC Device Model</h3></div><div class="col-lg-5"><p class="text-white line-clamp-3">In this video we will demonstrate interoperability of MARS RDMA Device Model with Nvidia RDMA.</p></div></div></div></div><div class="swiper-slide"><div class="video-card_mainCard__YvhQN" style="background-image:url(/_next/static/media/jr-korpa-9XngoIpxcEo-unsplash.3a28fc65.jpg)"><div style="height:100%" class="align-items-center row"><div class="col-lg-3"><div class="video-card-two__box mt-2"><img src="/_next/static/media/Ellipse 1.aa094e05.png" alt="" class="video-card_bgVideo__gPE7T"/><span class="video-card-two__box-btn video-popup"><i class="fa fa-play"></i></span></div></div><div class="col-lg-4"><h3>SONiC DASH compliant SmartNic</h3></div><div class="col-lg-5"><p class="text-white line-clamp-3">DreamBig proudly presented its SONiC DASH compliant SmartNic Demo at the Consumer Electronic Show 2023.</p></div></div></div></div><div class="swiper-slide"><div class="video-card_mainCard__YvhQN" style="background-image:url(/_next/static/media/jr-korpa-stwHyPWNtbI-unsplash.a687e7d5.jpg)"><div style="height:100%" class="align-items-center row"><div class="col-lg-3"><div class="video-card-two__box mt-2"><img src="/_next/static/media/Ellipse 1.aa094e05.png" alt="" class="video-card_bgVideo__gPE7T"/><span class="video-card-two__box-btn video-popup"><i class="fa fa-play"></i></span></div></div><div class="col-lg-4"><h3>MARS SmartNIC Device Model</h3></div><div class="col-lg-5"><p class="text-white line-clamp-3">In this demo we will demonstrate different (IPSec, Match/Action, MAC Filtering, Checksum Verification and RSS) offloads of MARS LAN Device Model..</p></div></div></div></div></div><div class="swiper-pagination" id="main-slider-pagination"></div></div></div></div></section><section id="company" class="about-counter pt-120"><div class="about-counter_bgImg__ta4Ff"></div><div class="custom-container container"><div class="row"><div class="col-lg-6"><div class="block-title"><p class="textPrimary">About the Company</p><h3 class="">Emerging Semiconductor <br/>Startup</h3></div><p class="about-counter_aboutText__h8H9G about-counter__text">DreamBig Semiconductor is an emerging semiconductor startup that is dedicated to providing comprehensive low cost, low latency and high throughput solutions for AI, Datacenters, 5G and Automotive Markets. Headquartered in San Jose, CA, USA. DreamBig Semiconductor has offices in different regions across the world for R&D cost optimization. DreamBig Semiconductor has also established strategic partnerships with global leaders in the ecosystem.<br/><br/></p><span class="font-bold text-xl">The DreamBig Semiconductor team has top innovators of Semiconductor industry with an unmatched proven track record of disruptive technologies.</span><div class="marginY-12"></div><div class=""><div class="about-counter_countDiv__nEVwW row"><div class="col-lg-4"><div class="about-counter__count "><h3 class=" flex items-center text-center space-x-2"><svg stroke="currentColor" fill="currentColor" stroke-width="0" viewBox="0 0 16 16" color="gray" class="about-counter_icon__ibMe5" style="color:gray" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path d="M15 14s1 0 1-1-1-4-5-4-5 3-5 4 1 1 1 1zm-7.978-1L7 12.996c.001-.264.167-1.03.76-1.72C8.312 10.629 9.282 10 11 10c1.717 0 2.687.63 3.24 1.276.593.69.758 1.457.76 1.72l-.008.002-.014.002zM11 7a2 2 0 1 0 0-4 2 2 0 0 0 0 4m3-2a3 3 0 1 1-6 0 3 3 0 0 1 6 0M6.936 9.28a6 6 0 0 0-1.23-.247A7 7 0 0 0 5 9c-4 0-5 3-5 4q0 1 1 1h4.216A2.24 2.24 0 0 1 5 13c0-1.01.377-2.042 1.09-2.904.243-.294.526-.569.846-.816M4.92 10A5.5 5.5 0 0 0 4 13H1c0-.26.164-1.03.76-1.724.545-.636 1.492-1.256 3.16-1.275ZM1.5 5.5a3 3 0 1 1 6 0 3 3 0 0 1-6 0m3-2a2 2 0 1 0 0 4 2 2 0 0 0 0-4"></path></svg><span class="about-counter_heading__pMueN"></span></h3><p class="about-counter_text__Ywr7h">Staff & Members</p></div> </div><div class="col-lg-4"><div class="about-counter__count"><h3 class=" flex items-center text-center space-x-2"><svg stroke="currentColor" fill="currentColor" stroke-width="0" viewBox="0 0 640 512" color="gray" class="about-counter_icon__ibMe5" style="color:gray" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path d="M353.8 54.1L330.2 6.3c-3.9-8.3-16.1-8.6-20.4 0L286.2 54.1l-52.3 7.5c-9.3 1.4-13.3 12.9-6.4 19.8l38 37-9 52.1c-1.4 9.3 8.2 16.5 16.8 12.2l46.9-24.8 46.6 24.4c8.6 4.3 18.3-2.9 16.8-12.2l-9-52.1 38-36.6c6.8-6.8 2.9-18.3-6.4-19.8l-52.3-7.5zM256 256c-17.7 0-32 14.3-32 32V480c0 17.7 14.3 32 32 32H384c17.7 0 32-14.3 32-32V288c0-17.7-14.3-32-32-32H256zM32 320c-17.7 0-32 14.3-32 32V480c0 17.7 14.3 32 32 32H160c17.7 0 32-14.3 32-32V352c0-17.7-14.3-32-32-32H32zm416 96v64c0 17.7 14.3 32 32 32H608c17.7 0 32-14.3 32-32V416c0-17.7-14.3-32-32-32H480c-17.7 0-32 14.3-32 32z"></path></svg><span class="about-counter_heading__pMueN"></span></h3><p class="about-counter_text__Ywr7h">Years of Experience</p></div></div><div class="col-lg-4"><div class="about-counter__count"><h3 class=" flex items-center text-center space-x-2"><svg stroke="currentColor" fill="currentColor" stroke-width="0" viewBox="0 0 24 24" color="gray" class="about-counter_icon__ibMe5" style="color:gray" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path d="M12 2C6.486 2 2 6.486 2 12s4.486 10 10 10 10-4.486 10-10S17.514 2 12 2zM4 12c0-.899.156-1.762.431-2.569L6 11l2 2v2l2 2 1 1v1.931C7.061 19.436 4 16.072 4 12zm14.33 4.873C17.677 16.347 16.687 16 16 16v-1a2 2 0 0 0-2-2h-4v-3a2 2 0 0 0 2-2V7h1a2 2 0 0 0 2-2v-.411C17.928 5.778 20 8.65 20 12a7.947 7.947 0 0 1-1.67 4.873z"></path></svg><span class="about-counter_heading__pMueN"></span></h3><p class="about-counter_text__Ywr7h">Gloabal Presence</p></div> </div></div></div></div><div class="col-lg-6"><div class="about-counter__image clearfix"><img src="/_next/static/media/cpu-bg.0c00279b.png" alt="" class="about-counter_zoomAnimation__s_KCP float-left"/></div></div></div></div></section><div id="products" class="products_productsSection__DeU4Q"><div class="products_bgImg___6fc9"></div><div class="custom-container container"><h2 class="products_heading__2wibd">Our Products</h2><div class="products_largeCards__WJBQ9"><div class="large-card_card__8mG7p large-card_left__Q0T0d undefined disappear"><div class="large-card_imageWrapper__2_t6c"><img class="large-card_image__x7dic" src="/_next/static/media/slider-1-1.c3472cc4.jpg" alt="DreamBig's Chiplet Hub"/></div><div class="large-card_content__pngAw"><h3>DreamBig's Chiplet Hub</h3><p class="undefined">DreamBig is a disruptive chiplet platform startup, specializing in high performance applications for AI, datacenter, and automotive markets. The company supports an open chiplet marketplace using standard die-to-die interfaces such as UCIe and BoW with standard AMBA protocols enabling customers to compose differentiated products from horizontal innovations across the industry vs. proprietary vertical solutions from single vendors.</p></div></div><div class="large-card_card__8mG7p large-card_right__VWRFR undefined disappear"><div class="large-card_imageWrapper__2_t6c"><img class="large-card_image__x7dic" src="/_next/static/media/nat-hwcMLF374mY-unsplash.7a8b8d3d.jpg" alt="DreamBig’s DPU/SmartNIC"/></div><div class="large-card_content__pngAw"><h3>DreamBig’s DPU/SmartNIC</h3><p class="undefined"> DreamBig’s DPU/SmartNIC is the next generation of networking technology, offering a powerful combination of flexible hardware and programmable accelerators, fostering the development of secure and high-performance network solutions tailored for large-scale data centers, cloud environments, storage systems, machine learning applications and edge computing. This multifaceted innovation enhances operational productivity while substantially reducing the total cost of ownership.</p></div></div><div class="large-card_card__8mG7p large-card_left__Q0T0d undefined disappear"><div class="large-card_imageWrapper__2_t6c"><img class="large-card_image__x7dic" src="/_next/static/media/slider-blog.5b6b6be4.png" alt="DreamBig VCPP"/></div><div class="large-card_content__pngAw"><h3>DreamBig VCPP</h3><p class="undefined">DreamBig VCPP (Virtual Chiplet Prototyping platform) provides a H/W S/W co-simulation environment for chiplets which allows to run multiple RTL simulations in VCS/Questasim, Linux driver or device emulation in Qemu, and connect to external NICs or other physicals cards or machine. This way we can perform benchmarking against the competition. We can connect any AI or CPU Chiplet to VCPP. Running RDMA against Nvidia DPU proves it well.</p></div></div></div><div class="products_smallCards__Co6Rh"><div class="small-card_card__9kNGq small-card_even__2uWjQ undefined "><div class="small-card_iconWrapper__U1Rq_"><svg stroke="currentColor" fill="currentColor" stroke-width="0" viewBox="0 0 24 24" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path fill="none" stroke-width="2" d="M12,22 C12,22 2.99999999,18 3,11 L3,5 L12,2 L21,5 C21,5 21,11 21,11 C21,18 12,22 12,22 Z M12,14 C13.6568542,14 15,12.6568542 15,11 C15,9.34314575 13.6568542,8 12,8 C10.3431458,8 9,9.34314575 9,11 C9,12.6568542 10.3431458,14 12,14 Z M12,8 L12,5 M12,17 L12,14 M6,11 L9,11 M15,11 L18,11 M8,7 L10,9 M14,13 L16,15 M16,7 L14,9 M10,13 L8,15"></path></svg></div><p>Security</p></div><div class="small-card_card__9kNGq small-card_odd__q8EoT undefined "><div class="small-card_iconWrapper__U1Rq_"><svg stroke="currentColor" fill="none" stroke-width="2" viewBox="0 0 24 24" stroke-linecap="round" stroke-linejoin="round" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path d="M20 16.2A4.5 4.5 0 0 0 17.5 8h-1.8A7 7 0 1 0 4 14.9"></path><circle cx="12" cy="17" r="3"></circle><path d="M12 13v1"></path><path d="M12 20v1"></path><path d="M16 17h-1"></path><path d="M9 17H8"></path><path d="m15 14-.88.88"></path><path d="M9.88 19.12 9 20"></path><path d="m15 20-.88-.88"></path><path d="M9.88 14.88 9 14"></path></svg></div><p>AI</p></div><div class="small-card_card__9kNGq small-card_even__2uWjQ undefined "><div class="small-card_iconWrapper__U1Rq_"><svg stroke="currentColor" fill="currentColor" stroke-width="0" viewBox="0 0 24 24" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><g id="Cloud_On"><path d="M21.917,13.484a4.381,4.381,0,0,0-5.19-4.26,6.281,6.281,0,0,0-11.75,2.19,3.237,3.237,0,0,0-2.66,2,3.433,3.433,0,0,0,.82,3.74c1.12,1.03,2.54.89,3.94.89h10.15a4.514,4.514,0,0,0,4.69-4.32Zm-4.65,3.56c-1.19.01-2.38,0-3.56,0-2.75,0-5.49.06-8.23,0a2.383,2.383,0,0,1-2.33-1.73,2.333,2.333,0,0,1,2.28-2.94.515.515,0,0,0,.5-.5,5.3,5.3,0,0,1,10.11-1.81.5.5,0,0,0,.56.23,3.366,3.366,0,0,1,4.33,3.32A3.489,3.489,0,0,1,17.267,17.044Z"></path></g></svg></div><p>NFV/SDN</p></div><div class="small-card_card__9kNGq small-card_odd__q8EoT undefined "><div class="small-card_iconWrapper__U1Rq_"><svg stroke="currentColor" fill="currentColor" stroke-width="0" viewBox="0 0 24 24" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path fill="none" stroke-width="2" d="M23,12 C23,18.075 18.075,23 12,23 C5.925,23 1,18.075 1,12 C1,5.925 5.925,1 12,1 C18.075,1 23,5.925 23,12 L23,12 Z M18,12 C18,8.691 15.309,6 12,6 C8.691,6 6,8.691 6,12 C6,15.309 8.691,18 12,18 C15.309,18 18,15.309 18,12 L18,12 Z M13,12 C13,11.448 12.552,11 12,11 C11.448,11 11,11.448 11,12 C11,12.552 11.448,13 12,13 C12.552,13 13,12.552 13,12 L13,12 Z"></path></svg></div><p>Hyperconverged</p></div><div class="small-card_card__9kNGq small-card_even__2uWjQ undefined "><div class="small-card_iconWrapper__U1Rq_"><svg stroke="currentColor" fill="currentColor" stroke-width="0" viewBox="0 0 24 24" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path fill="none" stroke-width="2" d="M2,5.07692308 C2,5.07692308 3.66666667,2 12,2 C20.3333333,2 22,5.07692308 22,5.07692308 L22,18.9230769 C22,18.9230769 20.3333333,22 12,22 C3.66666667,22 2,18.9230769 2,18.9230769 L2,5.07692308 Z M2,13 C2,13 5.33333333,16 12,16 C18.6666667,16 22,13 22,13 M2,7 C2,7 5.33333333,10 12,10 C18.6666667,10 22,7 22,7"></path></svg></div><p>Storage</p></div></div></div></div><section id="our-experts" class="our-experts_OurExperts__MDxi6"><div class="lgContainer container"><div class="our-experts_headDiv__bFHF2"><div class="our-experts_headDiv_left__9MdIx"><h6 class="our-experts_title__ltE0K">Our Team</h6><h2 class="our-experts_heading__qIxTu">Meet Our Experts</h2></div><div class="our-experts_headDiv_left__9MdIx"></div></div><div class="our-experts_productCards___2ov1"><div class="Person-card_PersonCard__t3zCZ undefined"><div class="Person-card_cardInner__ngYiP"><div class="Person-card_cardFront__PnmMq"><img class="Person-card_img__9juHq" src="/_next/static/media/person1.c62a702d.png" alt="person"/><div class="Person-card_button__Pz6tf"><h6 class="Person-card_name__JyFqQ">SEHAT SUTARDJA</h6><p class="Person-card_role__ik_Yy">Executive Chairman</p></div></div><div class="Person-card_cardBack__A_6Ex"><p class="Person-card_description__C0SPG">Sehat co-founded Marvell Technology Group in February 1995 and served as the CEO and Executive Chairman until 2016. For his unparalleled engineering, Sehat was awarded over 440 patents, recognized as Inventor of the Year by SVIPLA, and was named a Fellow of IEEE. He holds a PhD from UC Berkeley in Electrical Engineering and Computer Science.</p></div></div></div><div class="Person-card_PersonCard__t3zCZ undefined"><div class="Person-card_cardInner__ngYiP"><div class="Person-card_cardFront__PnmMq"><img class="Person-card_img__9juHq" src="/_next/static/media/person2.2b071b84.png" alt="person"/><div class="Person-card_button__Pz6tf"><h6 class="Person-card_name__JyFqQ">WEILI DAI</h6><p class="Person-card_role__ik_Yy">Executive Vice Chairwoman</p></div></div><div class="Person-card_cardBack__A_6Ex"><p class="Person-card_description__C0SPG">Weili co-founded Marvell Technology Group in February 1995 and served as the President until 2016. She was named “The World’s 100 Most Powerful Women” by Forbes Magazine in 2012 and awarded the Dr. Morris Change Exemplary Leadership Award by the Global Semiconductor Alliance. She holds a BSc from UC Berkeley in Computer Science.</p></div></div></div><div class="Person-card_PersonCard__t3zCZ undefined"><div class="Person-card_cardInner__ngYiP"><div class="Person-card_cardFront__PnmMq"><img class="Person-card_img__9juHq" src="/_next/static/media/Sohail2.e17ee00d.jpeg" alt="person"/><div class="Person-card_button__Pz6tf"><h6 class="Person-card_name__JyFqQ">SOHAIL SYED</h6><p class="Person-card_role__ik_Yy">CEO / President</p></div></div><div class="Person-card_cardBack__A_6Ex"><p class="Person-card_description__C0SPG">Sohail is president, CEO and founder of Dreambig semiconductor. Prior to DreamBig, Sohail, as serial entrepreneur, successfully started multiple companies including Questarium (Acquired by Marvell) and FIRQuest (Acquired by Corigine). Sohail earned his MBA from Cornell and holds 10 patents in the field of searching and compression.</p></div></div></div></div> </div></section><div id="bg-video" class="bg-image_productsSection__ErWxV"><div class="bg-image_bgImg___Z2cL"></div><div class="custom-container container"><video class="bg-image_video__kJRN_ " autoPlay="" loop="" playsInline="" muted=""><source src="https://dreambigsemi.com/wp-content/uploads/Dreambig%20Chiplet%20Platform.mp4" type="video/mp4"/>Your browser does not support the video tag.</video><button class="bg-image_muteButton__GYZAn"><svg stroke="currentColor" fill="currentColor" stroke-width="0" viewBox="0 0 24 24" height="36" width="36" xmlns="http://www.w3.org/2000/svg"><path d="M12 3.75v16.5a.75.75 0 0 1-1.255.555L5.46 16H2.75A1.75 1.75 0 0 1 1 14.25v-4.5C1 8.784 1.784 8 2.75 8h2.71l5.285-4.805A.75.75 0 0 1 12 3.75ZM6.255 9.305a.748.748 0 0 1-.505.195h-3a.25.25 0 0 0-.25.25v4.5c0 .138.112.25.25.25h3c.187 0 .367.069.505.195l4.245 3.86V5.445ZM16.28 8.22a.75.75 0 1 0-1.06 1.06L17.94 12l-2.72 2.72a.75.75 0 1 0 1.06 1.06L19 13.06l2.72 2.72a.75.75 0 1 0 1.06-1.06L20.06 12l2.72-2.72a.75.75 0 0 0-1.06-1.06L19 10.94l-2.72-2.72Z"></path></svg></button></div></div><section id="blogs-and-articles" class="articles-blog_ArticlesAndBlogs__HPlSy"><div class="articles-blog_bgImg__6li5Y"></div><div class="custom-container container"><h2 class="articles-blog_heading__pWd7O">Latest Blogs & Press Release</h2><div class="swiper"><div class="swiper-wrapper"><div class="swiper-slide"><div class="Product-card_ProductCard__Ght3X"><img class="Product-card_img__UPIg5" src="https://res.cloudinary.com/dexek3yz7/image/upload/v1726761868/dreambig/cyvi6mj1w0maaacliw4k.jpg" alt="product" width="100" height="100"/><div class="Product-card_textSection__A6oyD"><h6 class="Product-card_title__CCe5b line-clamp-1">NEXT-GENERATION CHIPLET-BASED DPU ARCHITECTURE</h6></div><button class="Product-card_button__3waM2"><svg stroke="currentColor" fill="none" stroke-width="2" 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Chiplet Platform</h6></div><button class="Product-card_button__3waM2"><svg stroke="currentColor" fill="none" stroke-width="2" viewBox="0 0 24 24" stroke-linecap="round" stroke-linejoin="round" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path d="m9 18 6-6-6-6"></path></svg> Read More</button></div></div><div class="swiper-slide"><div class="Product-card_ProductCard__Ght3X"><img class="Product-card_img__UPIg5" src="https://res.cloudinary.com/dexek3yz7/image/upload/v1726748513/dreambig/ewwaky6dfj7ll4vq0n8u.jpg" alt="product" width="100" height="100"/><div class="Product-card_textSection__A6oyD"><h6 class="Product-card_title__CCe5b line-clamp-1">DreamBig Semiconductor Participated in SmartNICs SUMMIT 2023</h6></div><button class="Product-card_button__3waM2"><svg stroke="currentColor" fill="none" stroke-width="2" viewBox="0 0 24 24" stroke-linecap="round" stroke-linejoin="round" height="1em" width="1em" xmlns="http://www.w3.org/2000/svg"><path d="m9 18 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The Emergence of Chiplet-based Data Processing Unit (DPU) Architectures\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eCloud Service Providers (CSPs) are in the process of revamping their data center architectures, driven by the emergence of optimized processors for domain-specific workloads, especially Data Processing Units (DPUs). The DPU has emerged as an autonomous coprocessor and as a result has taken over many of the compute and infrastructure processing functions; for example, server virtualization, networking, storage, and security, that are traditionally performed by the CPU.\u0026nbsp;One of the major goals behind deployment of DPUs is to have server CPUs wholly dedicated to run application workloads. As a result, DPUs could potentially enable optimum performance for various cloud data center use-cases, including hyperscale, telco, enterprise and hybrid clouds with improved security and reliability, and improved return on investment (ROI).\u003c/p\u003e\u003cp\u003eDPUs have been traditionally implemented by using monolithic system-on-chip (SoC) architecture. While the shift to smaller silicon geometries has enabled larger SoC devices with big caches and many cores, but each new silicon technology generation requires a huge investment and results in significantly higher development and die costs. Consequently, developing SoC-based DPUs supporting the range of required use cases is becoming commercially unappealing, especially in light of several important industry trends.\u003c/p\u003e\u003cp\u003eMoore’s Law provided consistent advances in transistor technology over decades that enabled chip vendors to meet the demands of monolithic SoC architectures, but only lately Moore’s law has witnessed a historic slowdown. As a result, transitioning to the next node has become much more costly while offering minimal advantage. Relatedly, due to the significant increase in cost in architecting SoCs, the industry is seeing the emergence of chip designs using several\u0026nbsp;small dies, or\u0026nbsp;\u003cem\u003echiplets\u003c/em\u003e, rather than one monolithic die.\u003c/p\u003e\u003cp\u003eThe use of chiplets for DPU architectures can enable the support of power and area goals while providing the flexibility and product modularity required to support different use cases in a single DPU package. A chiplet-based architecture can support an integrated DPU device which uses components developed using different silicon technologies while also providing innovative solutions that utilize best-of-breed components. As a result, the use of chiplets offers a cost-effective approach for providing DPUs that support a wide range of use cases.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003ch2\u003eSoC to Chiplet Transition Enables Moore’s Law Extension\u0026nbsp;\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eThe benefits provided by Moore’s Law through enabling steady advances in development of complex SoCs such as DPUs are starting to diminish. Multiplying transistor density now takes three or four years instead of two. Each boost in density comes with a dramatic increase in wafer expense, generating modest or no decrease in cost per transistor, a key principle of Moore’s Law. Speed and power increases have also lessened with each new evolution in transistor density or node. In short, transitioning to the next node has become much more costly while offering minimal advantage.\u003c/p\u003e\u003cp\u003eDue to the exponential increase in cost of developing leading-edge SoCs, only the very biggest suppliers have been able to develop monolithic chip designs for CPUs and DPUs. To compensate for soaring design costs and boost manufacturing yields, leading vendors have instead begun to adopt designs. Intel and Marvell have introduced chiplet-based products while AMD and Amazon Web Services (AWS) employ chiplets in new EPYC and Graviton server processors respectively. However, most of such early design chiplets have been designed exclusively in-house.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eFurther cost savings can come from creating different (heterogeneous) chiplets using different manufacturing nodes, which is impossible in a monolithic design.\u0026nbsp;For example, DPU chiplet designs could segregate I/O functions into a separate die manufactured in an older node. Some logic circuitry, such as accelerators, may not need to run at the same maximum clock rate as the main processor and thus can be fabricated in an intermediate node. Using older process technology can reduce the manufacturing cost of those chiplets as well as optimize aggregate power consumption of the aggregate chiplet-based DPU design.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003ch2\u003eDie-to-Die Interconnect Standardization Enables Heterogenous Chiplet-based Designs.\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eHeterogenous chiplet-based designs require standardizing die-to-die (D2D)\u0026nbsp;interconnects so that chiplets from multiple vendors may be seamlessly integrated. Otherwise,\u0026nbsp;each chiplet remains vendor-specific, which reduces the economic advantage of\u0026nbsp;disaggregating the design.\u0026nbsp;\u003c/p\u003e\u003cp\u003eOver the past few years, a broad range of cloud computing and semiconductor industry stalwarts have introduced open-source designs for die-to-die interconnects between chiplets, thus reducing costs and fostering a broader ecosystem of validated chiplets. In 2019 the Open Domain Specific Architecture (ODSA) subgroup within the Open Compute Project introduced a Bunch of Wires (BoW) die-to-die interconnects for providing a standardized connection between chiplets such as processor DPUs, and cores, memory, and I/O, that operates like on-die connections.\u003c/p\u003e\u003cp\u003eSimilarly, major semiconductor companies, including Intel, AMD, and Arm, have introduced the UCIe chiplet interconnect standard based on existing PCIe and CXL protocols which will also support latency and bandwidth requirements for rack-scale designs.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003ch2\u003eOptimum Support of Data Center Use Cases Requires Disaggregated Chiplet-based DPUs\u0026nbsp;\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eCloud operators can potentially reap tremendous benefits from DPU support for bare metal virtualization, while controlling and provisioning servers with isolation and security from their tenants.\u0026nbsp;DPUs can also possibly enable bare-metal data centers where the entire server hypervisor is offloaded to the DPU.\u003c/p\u003e\u003cp\u003eBy accelerating network services such as Open Virtual Switch (OVS) and virtual router (vRouter) functions, the DPU could allow data centers to also support Network Function Virtualization (NFV) and a range of additional security, filtering, and analytics use-cases.\u003c/p\u003e\u003cp\u003eThe DPU could also facilitate efficient pooling through permitting significantly higher utilization while offloading various networking, storage, and security functions. For example, through enabling pools of processors, pools of AI/GPU clusters and pools of storage, allows cloud operators to dynamically assign resources based on the specific AI application need; for example, inference or training.\u003c/p\u003e\u003cp\u003eDPUs with embedded hardware-based security processing may provide East-West firewalls to every server in the data center to meet the zero-trust imperative. DPUs may also be beneficial for offloading of inline or lookaside encryption security using IPsec and SSL/TLS for encryption/decryption of data-in-motion and data-at-rest.\u003c/p\u003e\u003cp\u003eWhile monolithic SoC-based DPUs may address the data center use cases discussed above, the time and cost required for designing such devices (which are only applicable to smaller market segments as compared to general purpose CPUs) can be very demanding. It requires deep expertise in networking, storage, and security protocol domains. In addition, the investment required to fabricate traditional monolithic architecture based DPUs using more sophisticated process nodes can be astonishing.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eDeveloping DPUs using chiplets with smaller die sizes can drastically cut semiconductor development times while lowering manufacturing costs.\u0026nbsp;DPUs built using chiplets also provide additional major benefits. Chiplet-based DPUs can utilize best-of-breed chips that incorporate components from multiple vendors, each with domain expertise in specific use case areas (e.g., processors, networking, security, and storage). As a result, cost and time-to-market for DPUs for specific use cases can be optimized through using smaller chiplet dies, different process nodes for specific chiplets as appropriate with a strong emphasis on core competency.\u003c/p\u003e\u003ch2\u003e\u003cbr\u003e\u003c/h2\u003e\u003ch2\u003eDreamBig Semiconductor: Next-Generation Chiplet-based Disruptive DPU Architecture\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eThe data center market is facing a strategic challenge as it attempts to meet the requirements for democratizing development and manufacturing of chiplet-based DPU silicon. Driven by standardized connectivity between chiplets, there is a critical need for an open ecosystem in which chiplets remain interoperable across different vendors while enabling support for complete end-to-end specifications to meet aggressive customer DPU use-cases. This is exactly where DreamBig Semiconductor, with its proven architecture and validated chiplet ecosystem, brings significant value.\u003c/p\u003e\u003cp\u003eDreamBig Semiconductor (DBS) is a pioneer in utilizing the chiplet approach to dramatically reduce the cost and time required for developing disaggregated DPUs for the full range of data-intensive use cases. DBS accomplishes this through offering chiplets for differentiated DPU functions, such as computer, networking, storage, and security functions, based on leading-edge process technology and through leveraging an established partner ecosystem of chiplet vendors for standard, common functions. As a result, customers can rapidly and cost-effectively develop chiplet-based DPUs which can optimally meet the needs of their specific data-intensive use cases.\u003c/p\u003e\u003cp\u003eThe DBS chiplet-based DPU architecture will provide end-users with greater flexibility, open new frontiers for component reuse and enable innovation on price, performance, and power consumption across the full continuum of DPU use-cases.\u0026nbsp;As a result, the DBS DPU architecture will allow\u0026nbsp;users to\u0026nbsp;bring together design IP and process technologies from an established ecosystem of vendors enabled not only by standardization of Die-to-Die (D2D) interfaces, but also through interoperability across different vendors and foundries while at the same time supporting multiple process nodes (both leading-edge and established) and packaging technologies.\u003c/p\u003e\u003cp\u003eTowards that goal, DBS is also focused on enabling a best-of-breed partner ecosystem of chiplet manufacturers to offer DPU users standardized, interoperable hardware as a critical priority. This ecosystem supports complete end-to-end specifications including protocols, packaging, testing, and manufacturing, to meet aggressive and diverse customer time-to-market, cost, and use-case requirements.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cblockquote\u003eSaqib jang\u003c/blockquote\u003e\u003cblockquote\u003eAuthor\u003c/blockquote\u003e\u003ch2\u003e\u003cbr\u003e\u003c/h2\u003e\u003c/body\u003e\u003c/html\u003e"])</script><script>self.__next_f.push([1,"22:T1925,"])</script><script>self.__next_f.push([1,"\u003chtml\u003e\u003chead\u003e\u003c/head\u003e\u003cbody\u003e\u003ch2\u003eDreamBig World Leading “MARS” Open Chiplet Platform Enables Scaling of Next Generation Large Language Model (LLM), Generative AI, and Automotive Semiconductor Solutions\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eDreamBig Semiconductor, Inc. today unveiled “MARS”, a world leading platform to enable a new generation of semiconductor solutions using open standard Chiplets for the mass market. This disruptive platform will democratize silicon by enabling startups or any size company to scale-up and scale-out LLM, Generative AI, Automotive, Datacenter, and Edge solutions with optimized performance and energy efficiency.\u003c/p\u003e\u003cp\u003eDreamBig “MARS” Chiplet Platform allows customers to focus investment on the areas of silicon where they can differentiate to have competitive advantage and bring a solution to market faster at lower cost by leveraging the rest of the open standard chiplets available in the platform. This is particularly critical for the fast-moving AI training and inference market where the best performance and energy efficiency can be achieved when the solution is application specific.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cblockquote\u003e\u003cspan style=\"color: rgb(34, 34, 34);\"\u003eDreamBig is disrupting the industry by providing the most advanced open chiplet platform for customers to innovate never before possible solutions combining their specialized hardware chiplets with infrastructure that scales up and out maintaining affordable and efficient modular product development,” said\u0026nbsp;Sohail Syed, CEO\u0026nbsp;of DreamBig Semiconductor.\u003c/span\u003e\u003c/blockquote\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003e\u003cspan style=\"color: rgb(34, 34, 34);\"\u003eDreamBig “MARS” Chiplet Platform solves the two biggest technical challenges facing HW developers of AI servers and accelerators – scaling up compute and scaling out networking. The Chiplet Hub is the most advanced 3D memory first architecture in the industry with direct access to both SRAM and DRAM tiers by all compute, accelerator, and networking chiplets for data movement, data caching, or data processing. Chiplet Hubs can be tiled in a package to scale-up at highest performance and energy efficiency. RDMA Ethernet Networking Chiplets provide unparalleled scale-out performance and energy efficiency between devices and systems with independent selection of data path BW and control path packet processing rate.\u0026nbsp;\u003c/span\u003e\u003c/p\u003e\u003cblockquote\u003e\u003cspan style=\"color: rgb(34, 34, 34);\"\u003e\u0026nbsp;“Customers can now focus on designing the most innovative AI compute and accelerator technology chiplets optimized for their applications and use the most advanced DreamBig Chiplet Platform to scale-up and scale-out to achieve maximum performance and energy efficiency,” said\u0026nbsp;\u003c/span\u003e\u003cstrong style=\"color: rgb(34, 34, 34);\"\u003eSteve Majors, SVP of Engineering\u003c/strong\u003e\u003cspan style=\"color: rgb(34, 34, 34);\"\u003e\u0026nbsp;at DreamBig Semiconductor. “By establishing leadership with 3D HBM backed by multiple memory tiers under HW control in Silicon Box advanced packaging that provides highest performance at lowest cost without the yield and availability issues plaguing the industry, the barriers to scale are eliminated.”\u003c/span\u003e\u003c/blockquote\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003ch2\u003eThe Platform Chiplet Hub and Networking Chiplets offer the following differentiated features:\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cul\u003e\u003cli\u003eOpen standard interfaces and architecture agnostic support for CPU, AI, Accelerator, IO, and Memory Chiplets that customers can compose in a package\u003c/li\u003e\u003cli\u003eSecure boot and management of chiplets as a unified system-in-package similar to a platform motherboard of chips\u003c/li\u003e\u003cli\u003eMemory First Architecture with direct access from all chiplets to cache/memory tiers including low-latency SRAM/3D HBM stacked on Chiplet Hubs and high-capacity DDR/CXL/SSD on chiplets\u003c/li\u003e\u003cli\u003eFLC Technology Group fully associative HW acceleration for cache/memory tiers\u003c/li\u003e\u003cli\u003eHW DMA and RDMA for direct placement of data to any memory tier from any local or remote source\u003c/li\u003e\u003cli\u003eAlgorithmic TCAM HW acceleration for Match/Action when scaled-out to cloud\u003c/li\u003e\u003cli\u003eVirtual PCIe/CXL switch for flexible root port or endpoint resource allocation\u003c/li\u003e\u003cli\u003eOptimized for Silicon Box advanced Panel Level Packaging to achieve the best performance/power/cost – an alternative to CoWoS for the AI mass market\u003c/li\u003e\u003c/ul\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003ch2\u003eCustomers are currently working with DreamBig on next generation devices for the following use cases:\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cul\u003e\u003cli\u003eHAI Servers and Accelerators\u003c/li\u003e\u003cli\u003eHigh-end Datacenter and Low-end Edge Servers\u003c/li\u003e\u003cli\u003ePetabyte Storage Servers\u003c/li\u003e\u003cli\u003eDPUs and DPU Smart Switches\u003c/li\u003e\u003cli\u003eAutomotive ADAS, Infotainment, Zonal Processors\u003c/li\u003e\u003c/ul\u003e\u003cblockquote\u003e\u003cspan style=\"color: rgb(34, 34, 34);\"\u003e“We are very proud of what DreamBig has achieved establishing leadership in driving a key pillar of the market for high performance, energy conscious, and highly scalable AI solutions to serve the world,” stated\u0026nbsp;\u003c/span\u003e\u003cstrong style=\"color: rgb(34, 34, 34);\"\u003eSehat Sutardja and Weili Dai, Co-founders and Chairman/Chairwoman\u003c/strong\u003e\u003cspan style=\"color: rgb(34, 34, 34);\"\u003e\u0026nbsp;of DreamBig. “The company has raised the technology bar to lead the semiconductor industry by delivering the next generation of open chiplet solutions such as Large Language Model (LLM), Generative AI, Datacenter, and Automotive solutions for the global mass market.”\u003c/span\u003e\u003c/blockquote\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eTo learn more, come see DreamBig technology solution demo January 9-12 at CES 2024 – The Most Powerful Tech Event in the World in The Venetian Expo, Bellini 2003 Meeting Room.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003ch2\u003eAbout DreamBig Semiconductor\u003c/h2\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eDreamBig, founded in 2019, is developing a disruptive and world leading Chiplet Platform that enables customers to bring to market the next generation of high performance, energy conscious, affordable, scalable, and composable semiconductor chiplet solutions for the AI revolution and digital world. The company specializes in high performance applications used for Large Language Model (LLM), Generative AI, Datacenter, Edge, and Automotive markets.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003eDreamBig provides the industry’s most advanced Chiplet Hub to scale-up compute/accelerator Chiplets, and the most advanced Networking Chiplets to scale-out.\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cp\u003e\u003cu\u003e \u003c/u\u003e\u003c/p\u003e\u003cp\u003e\u003cu\u003e \u003c/u\u003e\u003c/p\u003e\u003cp\u003e\u003cbr\u003e\u003c/p\u003e\u003cblockquote\u003eDreamBig Semiconductor Inc. || PR News Wire\u003c/blockquote\u003e\u003cblockquote\u003e\u003cstrong\u003eAuthor\u003c/strong\u003e\u003c/blockquote\u003e\u003c/body\u003e\u003c/html\u003e"])</script><script>self.__next_f.push([1,"23:T46d,\u003chtml\u003e\u003chead\u003e\u003c/head\u003e\u003cbody\u003e\u003cp\u003e\u003ca href=\"https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=4062440-1\u0026amp;h=682465429\u0026amp;u=https%3A%2F%2Fdreambigsemi.com%2F\u0026amp;a=DreamBig+Semiconductor%2C+Inc.\" rel=\"noopener noreferrer\" target=\"_blank\" style=\"color: inherit;\"\u003eDreamBig Semiconductor, Inc.\u003c/a\u003e\u0026nbsp;today unveiled “MARS”, a world leading platform to enable a new generation of semiconductor solutions using open standard Chiplets for the mass market. This disruptive platform will democratize silicon by enabling startups or any size company to scale-up and scale-out LLM, Generative AI, Automotive, Datacenter, and Edge solutions with optimized performance and energy efficiency.\u003c/p\u003e\u003cp\u003e\u003cspan style=\"color: rgb(55, 55, 55);\"\u003eTo learn more, come see DreamBig technology solution demo\u0026nbsp;January 9-12\u0026nbsp;at\u0026nbsp;\u003c/span\u003e\u003ca href=\"https://c212.net/c/link/?t=0\u0026amp;l=en\u0026amp;o=4062440-1\u0026amp;h=1630381738\u0026amp;u=https%3A%2F%2Fwww.ces.tech%2F\u0026amp;a=CES+2024+-+The+Most+Powerful+Tech+Event+in+the+World\" rel=\"noopener noreferrer\" target=\"_blank\" style=\"color: rgb(6, 51, 105); background-color: rgb(255, 255, 255);\"\u003eCES 2024\u003c/a\u003e\u003c/p\u003e\u003c/body\u003e\u003c/html\u003e"])</script><script>self.__next_f.push([1,"c:[\"$\",\"$L17\",null,{\"children\":[[\"$\",\"$L18\",null,{}],[\"$\",\"$L19\",null,{}],[\"$\",\"$L1a\",null,{}],[\"$\",\"$L1b\",null,{\"products\":[{\"_id\":\"66ea625ac13751dc3d7e945e\",\"title\":\"MARS SmartNIC Device Model - RDMA Demo\",\"description\":\"\u003chtml\u003e\u003chead\u003e\u003c/head\u003e\u003cbody\u003e\u003cp\u003e\u003cspan style=\\\"color: rgb(122, 122, 122);\\\"\u003eIn this video we will demonstrate interoperability of MARS RDMA Device Model with Nvidia RDMA.\u003c/span\u003e\u003c/p\u003e\u003c/body\u003e\u003c/html\u003e\",\"postedDate\":\"2024-09-18T05:17:14.413Z\",\"__v\":0},{\"_id\":\"66e24615043d0774d5cc0a5b\",\"title\":\"NVMe over Fabric (NVME-oF) demonstration at CES 2024\",\"description\":\"\u003chtml\u003e\u003chead\u003e\u003c/head\u003e\u003cbody\u003e\u003cp\u003eTest\u003c/p\u003e\u003c/body\u003e\u003c/html\u003e\",\"postedDate\":\"2024-09-12T01:38:29.701Z\",\"__v\":0}]}],[\"$\",\"$L1c\",null,{}],[\"$\",\"$L1d\",null,{}],[\"$\",\"$L1e\",null,{}],[\"$\",\"$L1f\",null,{}],[\"$\",\"$L20\",null,{\"blogs\":[{\"_id\":\"66ebc26e4c47c785a77b361e\",\"title\":\"NEXT-GENERATION CHIPLET-BASED DPU ARCHITECTURE\",\"description\":\"$21\",\"image\":\"https://res.cloudinary.com/dexek3yz7/image/upload/v1726761868/dreambig/cyvi6mj1w0maaacliw4k.jpg\",\"postedDate\":\"2024-09-19T06:19:26.457Z\",\"__v\":0},{\"_id\":\"66e197d46884127668b1f38c\",\"title\":\"DREAMBIG WORLD LEADING “MARS” OPEN CHIPLET PLATFORM UNVEILED AT CES 2024\",\"description\":\"$22\",\"image\":\"https://res.cloudinary.com/dexek3yz7/image/upload/v1726655190/dreambig/ezrk3nckyblpie0r9bfc.jpg\",\"postedDate\":\"2024-09-11T13:15:00.679Z\",\"__v\":0}],\"news\":[{\"_id\":\"66ebc5ecd99eec93f23e0cb3\",\"title\":\"DreamBig closes $75M Series B Funding Round\",\"description\":\"\u003chtml\u003e\u003chead\u003e\u003c/head\u003e\u003cbody\u003e\u003cp\u003e\u003cspan style=\\\"color: rgb(35, 35, 35);\\\"\u003eDreamBig Semiconductor Inc., a pioneer in high-performance accelerator platforms utilizing its industry-leading Chiplet Hub™ with 3D HBM, raised $75M in series B equity funding round.\u003c/span\u003e\u003c/p\u003e\u003cp\u003e\u003cspan style=\\\"color: rgb(35, 35, 35);\\\"\u003eThis round was co-led by the Samsung Catalyst Fund and the Sutardja Family. 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